Split and merge design flow concept for fast turnaround time of circuit layout design

ABSTRACT

A method and system is disclosed to improve the turnaround time to provide adequate time to meet project schedules in the event that adjustments or modifications to the design are necessary. A method for improving a turnaround time for design verification of a process database representing a semiconductor design includes the steps of (a) deriving a timing database and a (DNE) database from the process database; (b) performing, using the timing database, one or more design changes and one or more timing verifications and corrections to generate a modified timing database; (c) initiating, using the process database, physical validation of the semiconductor design prior to completion of step (b) to generate a modified DNE database; (d) merging the modified timing database with the modified DNE database to form a modified process database; and (e) performing, using the modified process database, one or more design verification checks of the semiconductor design.

FIELD OF THE INVENTION

The present invention relates generally to manufacturing techniques forthe design and development of mask-produced devices, and morespecifically to improving a turnaround time between layout and finalapproval of a device specification (e.g., a GDS2 database).

BACKGROUND OF THE INVENTION

The design, layout, test and manufacture of devices produced usingmasking processes like photolithography are very well known. Forexample, U.S. Pat. No. 6,171,731 (the '731 patent) issued to Medvedeva,et. al. entitled “Hybrid Aerial Image Simulation” provides a backgroundfor semiconductor fabrication. The specification of the '731 patent ishereby incorporated herein as though set forth in full by thisreference.

The classical approach to design an Application Specific IntegratedCircuit (ASIC) either in a fixed monolithic semiconductor technologysuch as gate arrays (GA) or standard cells (SC) or in a programmabletechnology like Field Programmable Gate Arrays (FPGAs) is divided intoseveral phases. FIG. 1 is a conventional design cycle model 100 thatforms a framework within which steps subsequent to a designspecification step 105 may be meaningfully integrated to produce afunctional, reliable product. After design specification step 105, thereare four major phases in design model 105, namely a high level synthesisstep 110, a logic synthesis step 115, a layout synthesis step 120 and amanufacturing step 125.

Design specification step 105 usually begins with or is initiated from aproduct requirement, which results from interaction between marketingand prospective costumers. An engineering response to the proposedproduct usually takes the form of a product definition document, whichaddresses issues of feasibility, general methods or techniques, cost,technical risk, trade offs between different approaches, and similaritems necessary to get product developments approvals. A general designspecification evolves into a precise technical description, where focusis on the external behavior of the circuits and communications betweenthe circuit and its external environment rather than an internalrealization.

Following design specification step 105 is high level synthesis step110. A main objective of high level synthesis step 110 is to begin withthe circuit specification details, transforming them into a high-leveldescription of how the various circuits will be structured, what majorfunctions need to be accomplished within the circuit and how thesefunctions can be realized as an interconnection of smaller circuitconstituents to meet the circuit specification details. High levelsynthesis step 110 takes an abstract behavioral representation of adigital system and produces a register-transfer level (RTL) structurethat realizes a given behavior. At this point in design model 100, eachfunctional block is defined in terms of interconnected registers,multiplexers, control elements, and the like. This is usually a criticalphase in the evolution of the circuit design, for the designer mustensure that the behavioral description being produced matches bothperformance and functional specifications. Describing a complex digitalsystem with hundreds of thousands of gates at the gate level is anextremely challenging task, and therefore, high level synthesis toolswere introduced. The VHSIC (very high speed integrated circuit) HardwareDescription Language, known as VHDL was adopted as an industry standardin about 1987 and is often used to describe hardware from the abstractbehavioral to the concrete level. VHDL was defined because a needexisted for an integrated design and documentation language tocommunicate design data between various levels of abstractions.

Following high level synthesis step 110 is logic synthesis step 115.Synthesis step 115 includes two subparts, an optimization step 115 a anda verification step 115 b, with optimization 115 usually beginning withthe RTL description and a collection of logic primitives. The primitivesare usually determined by a selected implementation style, and may be acollection of available gates, flip-flops, control functions, etc. Eachfunctional block described in a behavioral design phase is transferredinto a description that consists of logic primitives. They areinterconnected in a manner that satisfies both functional andperformance portions of the circuit specification. Logic synthesis step115 often begins with a straightforward transformation of the RTLdescription into an equivalent structure, expressed in terms of logicprimitives. A main objective of logic synthesis tools is to transformRTL description into an equivalent structure of logic primitives, suchthat either size and/or performance (e.g., critical delay) is minimized.Simulation verification step 115 b confirms the optimizations andgenerates testing protocols for the product design.

Following logic synthesis step 115 is layout synthesis step 120.Synthesis step 120 traditionally consists of two major steps, namelyplacement and routing. In a placement phase, logic primitives areassigned to physical location in the carrier environment selected forrealization of the circuit, with the objective being to easeinterconnection wiring design. Typically, placement algorithms attemptto minimize the total expected length of interconnect required for theresulting placement. In some design styles, such as for example gatearrays, other important issues must also be considered during theplacement phase. For example, in FPGAs limited routing resources,routing channel congestion and routing delays must also be consideredduring the placement phase. In a routing phase, placed logic primitivesare interconnected to form a desired logic design. Routing algorithmsneed not only ensure a one hundred percent routable design, but also tominimize routing congestions and a required routing space, as well asrouting delays (timing), that are imposed with the parasitic effects onrouting resources. After routing and timing, the design is verified bynumerous design checks referred to as physical verification.

After layout synthesis step 120, fabrication in manufacturing step 125depends on several things including a selected technology and designstyle. For a semi-custom design style such as standard cells and gatearray, masks are created in a technology center from a GDS2 database. Ifthe product is implemented in a programmable device, the devices areprogrammed in manufacturing step 125.

The last part of layout synthesis step 120 is the physical verificationbefore sending the GDS2 database to a mask vendor. Physical verificationincludes design rule checking and layout versus schematic checks. Oncephysical verification starts, a turnaround time for completing theverification for multimillion gate ASIC designs is very high. Thisturnaround time frequently becomes a bottle-neck in design flow model100.

In the timing closure part of the layout synthesis step 120, prior tothe physical verification, engineering changes are applied to the designto reach desirable performance and timing requirements. The productdesign parameters are maintained in a database, and the database islocked during the timing closure process. The DRC/LVS checking does notbegin until the database is unlocked following completion of the routingand timing. Serious problems could occur in model 100 if DRC/LVS startedprior to completing the routing and timing. These serious problems wouldarise due to mistakes in the physical implementation that would bediscovered very late in the design process. Discovering a seriousproblem late in the design process is likely to have a significantadverse impact on the overall project schedule.

As the projects become more and more complex, conventional model 100 canfurther make a project schedule unpredictable because the number ofDRC/LVS violations that must be corrected after layout is completedgrows to unmanageable size. For example, it is typical that apost-timing layout database includes over 80,000 DRC/LVS violations.Management is unable to predict when all of the tests will be conductedwith attendant violations cleared. The necessary and considerableresources for initiating these tests and clearing any violations cannotbe applied until late in the process. Thus turnaround time isunpredictable and typically is very long.

It is therefore desirable to improve the turnaround time to provideadequate time to meet project schedules in the event that adjustments ormodifications to the design are necessary.

SUMMARY OF THE INVENTION

A method and system is disclosed to improve the turnaround time toprovide adequate time to meet project schedules in the event thatadjustments or modifications to the design are necessary. A method forimproving a turnaround time for design verification of a processdatabase representing a semiconductor design includes the steps of (a)deriving a timing database and a (DNE) database from the processdatabase; (b) performing, using the timing database, one or more designchanges and one or more timing verifications and corrections to generatea modified timing database; (c) initiating, using the process database,physical validation of the semiconductor design prior to completion ofstep (b) to generate a modified DNE database; (d) merging the modifiedtiming database with the modified DNE database to form a modifiedprocess database; and (e) performing, using the modified processdatabase, one or more design verification checks of the semiconductordesign.

Splitting the database into a physical database and a timing databaseand processing both databases concurrently (one for routing and timingand the other for physical verification) improves the turnaround time ofthe design model employing this invention over conventional models.Changes made during timing verification are merged into the physicaldatabase, and the physical verification is completed to make thephysical verification accurate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a design cycle model that forms a framework within whichsubsequent steps in a design flow may be meaningfully integrated toproduce a functional, reliable product; and

FIG. 2 is a preferred embodiment of a portion of a design cycle modelthat improves turnaround time.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates generally to manufacturing techniques forthe design and development of mask-produced devices, and morespecifically to improving a turnaround time between layout and finalapproval of a device specification (e.g., a GDS2 database). Thefollowing description is presented to enable one of ordinary skill inthe art to make and use the invention and is provided in the context ofa patent application and its requirements. Various modifications to thepreferred embodiment and the generic principles and features describedherein will be readily apparent to those skilled in the art. Thus, thepresent invention is not intended to be limited to the embodiment shownbut is to be accorded the widest scope consistent with the principlesand features described herein.

FIG. 2 is a preferred embodiment of a portion of a design cycle model200 that improves turnaround time. Design cycle model 200 separates alayout database 205 into two database flows: a timing database flow 210and a physical database flow 215. Layout database 205 (as well asdatabases created for the timing flow 210 and the physical flow 215) isa database used by layout tools and includes all layout and timing datafor the product.

Layout synthesis step 120 shown in FIG. 1 may be further divided intothe following back end flow and tapeout flows.

The Back End Flow:

-   1. Loading in the initial design data (library information, Verilog    netlist, and synthesis constraints).-   2. Initial die size estimation and automatic floorplan creation.-   3. I/O placement.-   4. Automatic timing driven placement of block macros.-   5. Initial power routing (final power routing is done later).-   6. Timing driven placement and concurrent placement based    optimization through gate resizing and buffer insertion/deletion for    the standard cells.-   7. Clock tree synthesis and placement.-   8. Inserting Filler cells.-   9. Routing the design (final power routing, clock routing and signal    routing).-   10. Extracting parasitic capacitances.-   11. Post clock tree path optimization through gate resizing and    buffer insertion using parasitics.-   12. Incremental final routing to repair optimized nets.-   13. Post Routing Timing Analysis.-   14. Verification—connectivity and geometry.-   15. Output of final Verilog, DEF, SDF and GDSII.-   16. The GDSII from above is streamed in to the ICFB and after    generating all views for the same, the design is again streamed out.

The Tapeout Flow:

-   1. Running DRC (Design Rule Checks) on the GDSII.-   2. Running LVS (Layout Versus Schematic) on the GDSII.-   3. Layer Generation (LAYGEN) on the GDSII.-   4. Doing LDDCHECK (Layer Density Checks) on the design GDSII.-   5. Converting the dimensions of the design from CMOSX to CMOS8.-   6. Any physical changes to the design means the LVS and DRC checks    needs to be done again.

The preferred embodiment divides layout database 205 after step 7 (clocksynthesis and placement) of the backend flow has been completed. (Insome applications the separation may be able to be accomplished earlierin the back end flow, and in some instances the separation may occurlater.) As discussed above, layout database 205 is processed by twoflows, timing flow 210 and physical verification flow 215. Each flowuses a copy of the original layout database 205 with each flow lockingits database against any changes from outside its flow. In someapplications, these databases may not be duplicates of each other. Thedatabase used for the timing flow need only contain information used bythat process and the database for the physical verification need onlycontain information used by that process. The database copy used fortiming process 210 is referred to as the timing database and thedatabase copy used for the physical verification process 215 is referredto as the DNE database (DRC, Netlist versus schematic, and Ebeam). Forthe preferred embodiment, a GDS2 format is a format generated from alayout tool database (for example Avanti's Milkyway database). Anynecessary modifications are done inside the layout tool and not directlyin the GDS2 database. The DNE and Timing databases exist in the layouttool database. GDS2 is streamed out of the tool for DRC and LVS checks,but the corrections are done in the layout database.

Timing database flow 210 proceeds along the backend flow using thetiming database while physical database flow 215 immediately starts thetapeout flow process described above using the DNE database. Timingdatabase flow 210 applies engineering change orders (ECOs) (step 220),performs ECO routing (step 225), generates timing (step 230) andcompletes the layout (step 235) producing a list of changes and a finalplacement dumpfile. The ECOs include information about new addedstandard cells and their connection to other cells in the design.

Physical database flow 215 deletes analog and detailed routing (step250), fixes power map (step 255), performs analog routing (step 260) andproduces a design rule check (DRC) clean physical database with powerand custom routing complete (step 265). The DNE database has beencleaned from DRC and LVS issues related to the power mesh and customrouting in the design. Netlist and placement information changes fromthe timing process 215 are easier backfilled into the DNE database.

Thereafter, model 200 merges the results of the timing database flow 210into the DRC clean database from physical database flow 215 (step 270)into a modified layout database. This merger adds changes (ECOs forplacement and netlist modifications for example) made to the timingdatabase and backfills them into the verified DNE database. The unknownpart of the physical verification is verification of the signal routingchanges. Therefore a subpart of the DRC/LVS physical verification isrerun on the modified layout database (step 275) to complete the tapeoutprocess. Routers used for signal routing follow deterministic algorithmsand there is no risk of changes in the timing of the design after thesignal routing DRC/LVS physical verification.

In this approach only the information from the timing database aremerged in to the DNE database. This information includes the ECOs whichare basically changes applied to the logical netlist and the placementof the cells (including new added cells during the ECO). During mergingthe old cell placement from the DNE database is purged and overwrittenwith the new cell placement information and the respective logicalinformation in the netlist (ECO). Merging the DNE database in to thetiming database is not preferred, since the power routing that has beenfixed on the DNE database can cause shorts or DRC violations with theroutes in the timing database.

As shown in FIG. 2, process 200 drastically reduces the number ofend-of-schedule DRC tests, and any attendant violations that need to becleared. In the conventional model 100, the initial layout database canhave in excess of 80,000 DRC/LVS violations that must be checked. Bystarting physical verification after the timing processes have beencompleted in the previous conventional model, the tests must beinitiated and any violations cleared in a limited period. The presentinvention is able to detect and remove/clear most of the violationswhile the timing database is locked for changes so that the modifiedlayout database may have on the order of a hundred or less DRC/LVSviolations evaluated in the same period as was previously allocated forclearing over 80,000 DRC/LVS violations. This greatly reduced number ofviolations makes the period for finding and fixing the violationspredictable. In the meantime, design timing is closed without having anadditional impact on the overall turnaround time. Predictability ofproject schedules and allowing parallel work in complex ASIC projectsare key points to project success and customer satisfaction.

Although the present invention has been described in accordance with theembodiments shown, one of ordinary skill in the art will readilyrecognize that there could be variations to the embodiments and thosevariations would be within the spirit and scope of the presentinvention. Accordingly, many modifications may be made by one ofordinary skill in the art without departing from the spirit and scope ofthe appended claims.

1. A method for improving a turnaround time for design verification of aprocess database representing a semiconductor design, comprising: (a)deriving a timing database and a physical verification database from theprocess database, each containing a power mesh description for thesemiconductor device, a custom routing description for the semiconductordevice and standard cell power routine description for the semiconductordevice; (b) performing, using the timing database, one or more designchanges and one or more timing verifications and corrections to generatea modified timing database by (b1) deleting the custom routingdescription, (b2) fixing the vower mesh description to passverification, and (b3) adding a new custom routing description to passverification; (c) initiating, using the process database, physicalvalidation of the semiconductor design prior to completion of step (b)to generate a modified physical verification database; (d) merging themodified timing database with the modified physical verificationdatabase to form a modified process database; and (e) performing, usingthe modified process database, one or more design verification checks ofthe semiconductor design.
 2. The method of claim 1 wherein the processdatabase and the modified process database are in a layout tool format.3. The method of claim 1 wherein the timing database and the processdatabase are each a copy of the process database.
 4. The method of claim1 wherein deriving (a) is performed after the process database includesclock tree placement and synthesis.
 5. The method of claim 1 whereinperforming (b) completes Engineering Change Orders (ECOs), implementsECO routing, and generates a timing description of the semiconductordevice.
 6. The method of claim 5 wherein merging (d) further comprisesbackfilling modifications to the timing database into the physicalverification database upon completion of performing (b).
 7. The methodof claim 6 wherein performing (b) further comprises deleting the customrouting description, fixing the power mesh description to passverification and adding a new custom routing description to passverification.
 8. The method of claim 7 wherein performing (e) furthercomprises verifying signal routing.
 9. The method of claim 6 whereinperforming (e) further comprises verifying signal routing.
 10. Themethod of claim 5 wherein performing (b) further comprises deleting thecustom routing description, fixing the power mesh description to passverification and adding a new custom routing description to passverification.
 11. The method of claim 10 wherein performing (e) furthercomprises verifying signal routing.
 12. The method of claim 5 whereinperforming (e) further comprises verifying signal routing.
 13. Themethod of claim 1 wherein performing (e) further comprises verifyingsignal routing.
 14. The method of claim 1 wherein performing (e) furthercomprises verifying signal routing.
 15. A system for improving aturnaround time for design verification of a process databaserepresenting a semiconductor design, comprising: means for deriving atiming database and a physical verification database from the processdatabase, each containing a power mesh description for the semiconductordevice, a custom routing description for the semiconductor device andstandard cell power routing description for the semiconductor device;means for performing, using the timing database, one or more designchanges and one or more timing verifications and corrections to generatea modified timing database, and for deleting the custom routingdescription, fixing the power mesh description to pass verification, andadding a new custom routing description to pass verification; means forinitiating, using the process database, physical validation of thesemiconductor design prior to completion of the design change and timingverification to generate a modified physical verification database;means for merging the modified timing database with the modifiedphysical verification database to form a modified process database; andmeans for performing, using the modified process database, one or moredesign verification checks of the semiconductor design.